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Ordering number: ENN6522
Monolithic Linear IC
LA17000M
Tuner System IC with Built-in PLL for Car Audio Applications
Overview
The LA17000M is an all-in-one car tuner IC that incorporates a PLL frequency synthesizer and all functions of an AM/FM tuner in a single chip. By combining two chips, a PLL (LC72144 equivalent) and an FM tuner IC (LA1781M equivalent) into a single chip (*PLL + AM (up conversion) + FMFE + IF + NC + MCP + MRC), and as a result of optimal chip partitioning, the LA17000M improves the performance of car tuner systems, eliminates adjustments, and provides high reliability, all at a lower cost.
Package Dimensions
unit: mm
3255-QFP80
[LA17000M]
17.2
60 61
41 40
* PLL on chip * ADC (6 bits, 1 channel) * IF counter and I/O port on chip permit simplification of the interface. * Supports AM double conversion. * Enhanced noise countermeasures * Excellent tri-signal characteristics * Improved medium and weak electric field NC characteristics * Improved separation characteristics * Anti-birdie filter on chip (analog/digital output) * Multipath sensor output (analog/digital output) * Cost-saving features * AM double conversion (Up conversion method) * Enhanced FM-IF circuit (When there is interference from adjacent frequencies, the software handles switching of the CF between wide and narrow automatically.) * Because deviations in IF gain are only 1/3 that of earlier devices, adjustment is simplified when this IC is incorporated into a set; this IC also includes a shifter pin for VSM adjustment. * Suited for smaller devices * Permits high-frequency signal line processing in a tuner pack. * Easily conformes to FCC standards
3.0max
80 1
(0.83)
(2.7)
21
0.65 0.25
20
14.0 17.2
Features
0.15
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
62901RM (II) No. 6522-1/54
0.1
SANYO: QFP80 (14 x 14)
0.8
14.0
LA17000M Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCC1 max VCC2 max VDD max Pd max Topr Tstg Conditions Pins 6, 56, and 77 Pins 7, 61, 70, 75, and 76 Pin 19 Ta 85C, * With board Ratings 8.7 12.0 6.0 950 -40 to +85 -40 to 150 Unit V V V mW C C
* Specified board: 114.3 x 76.1 x 1.6 mm3, glass epoxy Operating Conditions at Ta = 25C
Parameter Recommended supply voltage Operating supply voltage range Symbol VCC VCC op VDD op Pin 19 Conditions Pins 6, 7, 56, 61, 70, 75, 76, and 77 Ratings 8.0 5.0 7.5 to 8.5 4.5 to 5.5 Unit V V V V
Tuner Block Operating Characteristics at Ta = 25C, VCC = 8.0 V, VDD = 5.0 V, in the specified Test Circuit
Parameter [FM characteristics] FM IF input Current drain Demodulated output Channel balance Total harmonic distortion Signal-to-noise ratio IF AM suppression ratio IF Muting attenuation CB ICCO-FM No input, I56 + I61 + I70 + I75 + I76 + I79 10.7 MHz, 100 dBV, 1 kHz, 100%mod, pin 15 output 10.7 MHz, 100 dBV, 1 kHz, ratio of pin15 and pin 16 10.7 MHz, 100 dBV, 1 kHz, 100% mod, pin 15 10.7 MHz, 100 dB, 1 kHz, fm = 1 kHz, pin 15 at 30% AM 10.7 MHz, 100 dBV, 1 kHz, attenuation on pin 15 when V49 = 0 2 V 10.7 MHz, 100 dBV, 1 kHz, attenuation on pin 15 when V49 = 0 2 V *Note 1 10.7 MHz, 100 dB V, 1 kHz, attenuation on pin 15 when V49 = 0 2 V *Note 2 10.7 MHz, 100 dB, L + R = 90%, pilot = 10%, pin 15 output ratio Pilot modulation at which V17 < 0.5 V Pilot modulation at which V17 > 3.5 V 10.7 MHz, 100 dBV, L + R = 90%, pilot = 10%, pin 15 10.7 MHz, 100 dBV, pilot = 10%, pin 15 signal/PILOT-LEVEL leak DIN AUDIO 10.7 MHz, 100 dBV, L - R = 90%, pilot = 10%, V44 = 3 V 0.6 V, pin 15 10.7 MHz, 100 dBV, 10 kHz, L + R = 90%, pilot = 10%, V45 = 3 V 0.6 V, pin 15 10.7 MHz, 100 dBV, 10 kHz, L + R = 90%, pilot = 10%, V45 = 3 V 0.1 V, pin 15 1.2 60 220 -1 98 330 0 0.4 75 55 3 13 26 25 82 68 8 18 31 35 4.1 3.1 0.4 12 1 1 6 22 5 5 10 9 9 14 1.2 6.6 13 23 36 110 445 +1 1 mA mVrms dB % dB dB dB dB dB dB % % % dB dB dB dB Symbol Conditions min Ratings typ max Unit
THD-FMmono 10.7 MHz, 100 dBV, 1 kHz, 100% mod, pin 15 S/N-FM IF AMR IF Att-1 Att-2 Att-3
Separation Stereo ON level Stereo OFF level Main total harmonic distortion Pilot cancellation SNC output attenuation HCC output attenuation
Separation ST-ON ST-OFF THD-Main L PCAN AttSNC AttHCC-1 AttHCC-2
Continued on next page.
No. 6522-2/54
LA17000M Continued from preceding page.
Ratings Parameter Input limiting voltage Muting sensitivity SD sensitivity Symbol VIN-LIM VIN-MUTE SD-sen1 FM SD-sen2 FM IF counter buffer output VIFBUFF-FM1 VIFBUFF-FM2 Signal meter output VSM FM-1 VSM FM-2 VSM FM-3 VSM FM-4 Muting bandwidth Muting drive output [FM FE Block] N-AGC on input W-AGC on input Conversion gain VNAGC VWAGC A. V1 A. V2 Oscillator buffer output [NC Block] NC input (pin 30) Gate time Noise sensitivity [MRC Block] MRC output MRC operating level MRC sensor output VMRC MRC-ON V42 = 5 V Input level on pin 48 that is below pin 42 = 5 V and pin 43 = 2 V, f = 70 kHz 2.1 22 2.25 33 1.5 2.1 15 105 50 47 0.6 3.4 170 87 78 160 55 52 0.5 1 4.5 210 93 84 99 90 1.2 1.4 5.9 220 60 2.9 2.4 44 1.9 V mVrms V V dB mVrms mVrms dB % V V mVrms dBV dBV
GATE
Conditions 10.7 MHz, 100 dBV, 30% mod, IF input that decreases the input reference output by -3 dB IF input level non-mod when V49 = 2 V IF input non-mod (at least 100 mVrms) at which the IF count buffer output turns on 10.7 MHz, 100 dBV, non-mod, pin 38 output, during SEEK 10.7 MHz, 100 dB V, non-mod, pin 38 output, during RDS mode No input, pin 42 DC output non-mod 50 dB, pin 42 DC output non-mod 70 dB, pin 42 DC output non-mod 100 dB, pin 42 DC output non-mod 100 dBV, when V49 = 2 V Bandwidth non-mod 100 dBV, 0 dB, pin 49 DC output non-mod 83 MHz, non-mod, input at which pin 2 is 2.0 V or less 83 MHz, non-mod, input at which pin 2 is 2.0 V or less (when KEYED-AGC is 4.0 V) 83 MHz, 80 dB, non-mod, FECF output 83 MHz, 80 dB, non-mod, 5 V applied to CF (pin 10), FECF output No input, pin 5 output f = 1 kHz, 1 s, 100 mVp-o pulse input 1 kHz, 1 s pulse input that starts noise canceller operation. Measured at Pin 30.
min 29 19 48 48 145 145 0.0 0.65 2.4 4.9 140 0.00 72 90 9 13 51
typ 36 27 56 56 245 245 0.1 1.6 3.2 5.8 210 0.1 79 97 13 17 67 15 18
max
Unit dBV
35 64 64 330 330 0.3 2.4 4.2 6.5 280 0.3 86 104 17 21 102
dBV dBV dBV mVrms mVrms V V V V kHz V dBV dBV dB dB mVrms s mVp-o
BW-MUTE VMUTE-100
VOSCBUFFFM
SN
VMRC-sensor1 V42 = 5 V, pin 34 output VMRC-sensor2 V42 = 5 V, pin 48 output, f = 70 kHz, 100 mVrms
[AM Characteristics] AM ANT input Practical sensitivity Detection output AGC-F.O.M Signal-to-noise ratio Total harmonic distortion Signal meter output Oscillator buffer output Wideband AGC sensitivity S/N-30 VO-AM VAGC-FOM S/N-AM THD-AM VSMAM-1 VSMAM-2 W-AGCsen1 W-AGCsen2 1 MHz, 30 dBV, fm = 1 kHz, 30% mod, pin 15 1 MHz, 74 dBV, fm = 1 kHz, 30% mod, pin 15 1 MHz, 74 dBV, output reference, input width at which output drops by 10 dB, pin 15 1 MHz, 74 dBV, fm = 1 kHz, 30% mod 1 MHz, 74 dBV, fm = 1 kHz, 80% mod 1 MHz, 30 dBV, non - mod 1 MHz, 120 dBV, non - mod 1.4 MHz, input when V62 = 0.7 V 1.4 MHz, input when V62 = 0.7 V (during SEEK)
VOSCBUFFAM-1 No input, pin 5 output
Continued on next page.
No. 6522-3/54
LA17000M Continued from preceding page.
Parameter SD sensitivity Symbol SD-sen1AM SD-sen2AM IF buffer output VIFBUFF-AM Conditions 1 MHz, ANT input level at which IF count output turns on 1 MHz, ANT input level at which SD pin turns on 1 MHz, 74 dBV, non-mod, pin 38 output min 27 27 150 Ratings typ 33 33 220 max 39 39 Unit dBV dBV mVrms
PLL Block Allowable Operating Ranges at Ta = -40 to +85C, VDD = 5 V, VSS = 0 V
Parameter High-level input voltage Low-level Input voltage Output voltage Input amplitude Symbol VIH1 VIL1 VO1 VO2 fIN1 fIN2 fIN3 Guaranteed crystal oscillator ranges Input amplitude X'tal VIN1 VIN2-1 VIN2-2 VIN3-1 VIN3-2 Data setup time Data hold time Clock low-level time Clock high-level time CE wait time CE setup time CE hold time Data latch change time Data output time tSU tHD tCL tCH tEL tES tEH tLC tDC tDH Conditions CE, CL, DI, I/O-1, I/O-2 CE, CL, DI, I/O-1, I/O-2, SDSTSW DO I/O-1, I/O-2 XIN; Sine wave, capacitor coupled PLLIN; Sine wave, capacitor coupled HCTR; Sine wave, capacitor coupled XIN, XOUT; CI 70 (X'tal: 10.25, 10.35 MHz); Note 1 XIN PLLIN; 10 f < 130 MHz; Note 2 PLLIN; 130 f <160 MHz; Note 2 HCTR; 0.4 f < 25 MHz: Serial data; CTC = 0: Note 3 HCTR; 8 f <12MHz: Serial data; CTC = 1: Note 4 DI, CL: Note 5 DI, CL: Note 5 CL: Note 5 CL: Note 5 CE, CL: Note 5 CE, CL: Note 5 CE, CL: Note 5 Note 5 DO, CL; Dependent on pull-up resistance, board capacity: Note 5 DO, CL; Dependent on pull-up resistance, board capacity: Note 5 Ratings min 2.2 0 0 0 1 10 0.4 10.1 200 40 70 40 70 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.2 0.2 typ max VDD + 0.3 0.8 6.5 13 8 160 25 10.5 1500 1500 1500 1500 1500 Unit V V V V MHz MHz MHz MHz mVrms mVrms mVrms mVrms mVrms s s s s s s s s s s
Note 1:
Recommended CI value for crystal oscillator CI 70 (X'tal: 10.25, 10.35 MHz) However, because the characteristics of the X'tal oscillation circuit depend on the board and circuit constants, we recommend requesting that the X'tal manufacturer perform the evaluation. Note 2: Refer to the program divider configuration. Note 3: Serial data: CTC = 0 Note 4: Serial data: CTC = 1 Note 5: Refer to the serial data timing.
No. 6522-4/54
LA17000M PLL Characteristics Electrical Characteristics at Ta = 25C, VDD = 5 V, VSS = 0 V
Parameter Built-in feedback resistors Symbol Rf1 Rf2 Rf3 Hysterisis width High-level output voltage Low-level output voltage VHIS VOH1 VOH2 VOL1 VOL2 VOL3 XIN PLLIN HCTR CE, CL, DI PD1, PDS, SEEKSW; IO = -1 mA XBUF; IO = -0.5 mA PD1, PDS, SEEKSW; IO = -1 mA XBUFF; IO = -0.5 mA I/O-1 to I/O-2; IO = 1.0 mA I/O-1 to I/O-2; IO = 2.5 mA I/O-1 to I/O-2; IO = 5.0 mA I/O-1 to I/O-2; IO = 9.0 mA VOL4 High-level input current IIH1 IIH2 IIH3 IIH4 Low-level input current IIL1 IIL2 IIL3 IIL4 Output off leakage current High-level 3-state off leakage current Low-level 3-state off leakage current Input capacitance A/D converter linearity error Pull-down transistor on resistance Supply current IOFF1 IOFF2 IOFFH IOFFL CIN Err Rpd1 IDD1 MRC SENSOR AUTO ADJ (MOS) PLLIN VDD; X'tal = 10.25 MHz, fIN2 = 160 MHz, VIN2 = 70 mVrms, fIN3 = 25 MHz, VIN3 = 40 mVrms VDD; PLL block halt (PLL INHIBIT), X'tal OSC operation (10.25 MHz) VDD ; PLL block halt, X'tal OSC halt -0.5 80 200 10 DO; IO = 5.0 mA CE, CL, DI; VIN = 6.5 V I/O-1 to I/O-2; VIN = 13 V XIN; VIN = VDD PLLIN; VIN = VDD CE, CL, DI; VIN = 0 V I/O-1 to I/O-2; VIN = 0 V XIN; VIN = 0 V PLLIN; VIN = 0 V I/O-1 to I/O-2; VO = 13 V DO; VO = 6.5 V PD1, PDS; VIN = VDD PD1, PDS; VIN = 0 V 0.01 0.01 6 +0.5 600 15 2 4 2 4 VDD-1.0 VDD-1.5 1 1.5 0.2 0.5 1 1.8 1 5 5 11 22 5 5 11 22 5 5 200 200 Conditions Ratings min typ 1 500 250 0.1VDD max Unit M k k V V V V V V V V V V A A A A A A A A A A nA nA pF LSB k mA
IDD2 IDD3
5
10 3
mA mA
No. 6522-5/54
LA17000M
16V/47F
SYS-PS+15V
+
0.01F 0.01F
SYS-PS-GND
16V/47F
+
G
--15V
10k
SYS-PS---15V DZ1 SYS-PS+12V CENTER-MATER
I O L79MO5T
--5V --15V +12V +15V 0.01F
1M
0.1F
+15V
0.1F
100k
SVC203
10k
16V/1F
30k
16V/100F
22F 0.22F
+
82pF
AM-STREO-OUT AM-STREO-OUT-GND
6.8k
50
NC NC 5 7 1 +3 6 --2 4 0.1F --15V
750pF
20k
NC NC 8 7 1 +3 6 --2 5 0.1F 4 --15V
SW12
G
0.01F 0.01F
DET-ADJ
+5V
1F
SEP-VOL -H SEP-VOL -L
L78MO5T I O
+15V
MUTE MRC-IN SIGNAL-MATER-Z DET-OUT NC-IN NC-IN-GND SW11
Test Circuit
43k
10k 8200pF 10k
P1
100k
82pF
1F
+
100k
5V VDDSNC/HCC1
10k
100 k
100k
SW09 SW08 MRC-OUT
2200pF
0.22F
240k
1F
10k
15k 0.01F 1F
0.1F 82pF 10k
1F
SIGNAL-MATER-1
IF AGC
0.047F
PHASE COMP
0.22F
60
AM FT +5V 180pF 0.01F 7 50 1st-IF-OUT 6 4 0.022F
1M 3.3F 1k
59
PILOT DET
58
AM LC
57
C-HCC
56
VCC
55
KEYED AGC
54
FM SD
53
VREF
52
QD IN
51
QD OUT
50
AFC IN
49
MUTE
48
FM S-METER MRC IN
47
DET OUT
46
NC IN
45
HCC
44
SNC
43
MRC OUT
42
AM/FM S-METER
41 40
5.6k
61
1F GND 39 U +5V 7 3
1M CR
62 AM ANTD/WIDE AGC 63 FM MUTE ADJ 64 RF AGC 65 2nd MIX IN
+3 --2
IF COUNT BUFF SEEK/STOP SELECT 38 0.022F
912kHz
CC
0.01F --5V SW13 112NME SW14 330
50 47k
MPX VCO 37 VR PC OUT 36 PC IN 35 MRC SENSOR OUT ADC 0 34 SEEKSW 33 HCTR 32 1000pF 1F 0.01F
2
+ 0.01F 50 6
CC 0.01F CR
--
4
MPX-FREO
10.7Hz 0.022F
330
66 FM IF BYPASS 67 FM IF IN 68 AM IF IN 69 1st IF OUT 70 AM MIX OUT
--5V
P1
33k
47k 47k
FM-IF-INPUT
450kHz
10.7Hz
1M
0.022F
112LDA
0.022F 47k
U +5V 7 3 2
CC
SW07 MRC-SENSOR-OUT
+ 0.01F 50 6
CC 0.01F
50
--
4
CR
IF-COUNT-BUFF
180pF 18k
150
71 AM SD ADJ/WIDE AGC IN 72 1st IF (WIDE)
LA17000M
I/O1 31 DO 30 CL 29 CI 28 CE 27 X OUT 26 X IN 25 I/O2 24 XBUFF 23
--5V
IF-COUNT-IN
10.7MHz 200k 30k
k k
82pF 82pF
73 AM RF AGC OUT 74 NARROW AGC IN/MUTE ATT ADJ 75 MIX OUT 76 MIX OUT 77 FE VCC 78 1st IF IN (NARROW)
9 1 8 2 7 3 6 712-12 4 1025MHz
16V/100F
+
0.022F
0.022F 100H
15pF
0.022F
SW40 SW41 RF-MIX-VCC RF-MIX-VCC-G
68pF
0.022F
+12V
200
30
33
NC 22pF 22pF
50
SW16 IO1 DO DUT-CCB-DI DUT-CCB-CL DUT-CCB-CE
150
2.2H
AM-VCC C FC18 15pF
33mH
15pF 560
X-IN
SW17 IOZ 0.022F
1M
B 100H
0.022F 100k 65pF
OSC BUFFER
0.022F
SDSTSW
LPF OUT
PLL VDD
NC Sens
Lch OUT
AM OSC
NC AGC
10k
FMOSC
Rch out
AM/FM
PLL IN
18pF
10pF
80 FM MIX IN
30k
FE GND
30
Gore OUT
XBUFF IN
5pF
FM RF AGC
AM-ANT-INPUT
MPX Pdot IN
8pF
NC MPX GND
G
D S
+
16V/47F
10.7Hz
0.022F
E
79 AM 1st MIX IN
PDS 22 10k PLL VSS 21 SOFP80 16V/1F
+
U +5V 7 3 2
CC
+ 0.01F 50 6
CC 0.01F CR
--
4
2nd-OSC-BUFF
100k
1SV234
AM-ANT-DUMP
30
0.022F
1000pF
10pF
FM ANTD
100pF
1SV234
510
0.022F
3SK263
100k 180k 100pF
+
50
100H
FM-ANT-INPUT
0.022F 350
0.022F 270pF P1 0.015F 0.015F
PD1 10k
16V/10F 0.1F
2.2k 10k D G S 2SK583
0.01F
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
--5V
VT-OUT PLL VCC
1000pF
25
6pF
30k
16V/100F
30pF
30k
1M 0.47F 51k 30pF
NC
1SV234
0.1F
P1
SW01 FM-ANT-DUMP
100 1SV234
6800pF
51k
+15V 0.1F 7 NC 3+ 5 1 NC 2 6 -- 4
30 k
FM-AGC
0.022F
200k
3.3F
10k
112LDA
0.01F
150pF 112LDA
+
PLL -VCC
--15V 0.1F
0.01F
50
1M
50 CR
OSC-BUFF-OUT
0.01F 6 CC
CF SW
4 0.01F --5V
NC-HPF-OUT
L-CH-OUT NC-LPF-OUT R-CH-OUT ST-SD
50
+ --2
3
NC NC 5 7 1 +3 6 --2 4 0.1F --15V
SW02
0.01F
1000pF
7
U 0.1F
+15V
+
GATE-OUT
PLL-IN SW06
SW03
SW04
SW05
FM-VCC
SW18
VF/IMZ-G VF/IMZ-S VF/IMZ-F
16V/100F
100pF
FM-MIX-INPUT
CC
+5V
FMIF AM NC MPX VCC
A13289
No. 6522-6/54
LA17000M [FM IF Selectivity Switching Circuit] Features 1) Comprises an FM/AM one-chip system. 2) Up conversion method is adopted for AM. 3) Uses an IF filter with a center frequency that is the same as the middle frequency of FM. 4) Uses a narrowband filter in AM mode. 5) Uses a narrowband filter in FM mode only during SEEK or when there is interference from adjacent frequencies. 6) Uses a wideband filter for normal reception in FM mode. 7) For an RDS AF search, switches to a narrowband filter and detects SD. 8) High sensitivity for detecting interference from adjacent frequencies. Advantages 1) This FM/AM one-chip tuner system (an IC that includes a microcontroller interface) allows for improved adjacent frequency interference characteristics without increased cost. 2) Prevents SD and IF count misdetection (station detection) during seek search, RDS AF search, and auto memory operations. 3) Permits adoption of an IC for certain functions without increasing the number of IC pins. 4) CF selectivity can be switched by the software in the microcontroller that controls the tuner, making it easy to achieve performance differentiation through the software. (The software can freely set the CF switching timing and conditions.) 5) Detects the radio wave status in the field through detection of SD, desired station field intensity, IF count output, and adjacent station field intensity. This IC offers improved adjacent frequency interference characteristics by switching the CF automatically when interference is being generated from an adjacent frequency.
[IF Band Switching Circuit] Purpose This AM/FM one-chip tuner IC automatically switches the FM selectivity, prevents misdetection during SEEK operations, and offers improved adjacent frequency interference characteristics without any increase in cost. New Technological Features 1. Comprises an AM/FM one-chip IC. 2. Because the narrowband CF that is used by the AM UP conversion system is also used for FM, additional external components required by earlier systems can be eliminated. 3. Uses a wideband CF during normal FM reception for high sound quality. 4. Uses a narrowband CF for AM reception, and if interference is being generated from adjacent frequencies during FM reception. 5. Uses a narrowband CF during SEEK and RDSAF search operations, preventing misdetection of SD and IF count due to adjacent stations. 6. CF switching is performed at the first IF amp input, and the amp gain is adjusted automatically to a suitable level according to the CF band form AM/FM or FM. 7. Switching of the CF input and the first IF amp gain is controlled by a microcontroller through the interface. The pins that are controlled are connected to the I/O ports of the microcontroller, and are controlled by the microcontroller's internal software. 8. Detection of adjacent frequency interference during FM reception is based on S-meter output, SD, and IF count output. The IF count buffer frequency fluctuates when interference is being generated from adjacent frequencies. This fluctuation is used to make the detection of interference from adjacent frequencies possible. (Related patents have been applied for.) Conventional Technologies 1. Comprised of a dedicated IC for IF band switching, or of multiple ICs. 2. None of the AM/FM all-in-one chip systems include the functions provided by the LA17000M. 3. Requires a narrowband CF especially for FM, resulting in increased costs. (Does not share the AM narrowband CF.) 4. Because CF switching control is handled by analog circuits or logic circuits, the switching timing can only be controlled through uniform conditions. Control by software is not possible.
No. 6522-7/54
LA17000M Conceptual Diagram of the FM-IF Band Switching System
Wideband filter FM RF Mixing Wideband filter Narrowband filter
SL
Limiter amp
FM DET
IF counter
Local oscillation Control circuit
VCC LO
A13290
Field intensity
Level Wideband A Narrowband
10.7
f (MHz)
A13291
Fud Fd
B
10.7
f (MHz)
A13292
C
FdL
Fd
FdH
A13293
D
FdL
Fd
FdH
A13294
No. 6522-8/54
LA17000M I/O Port Assignment Table
I/O-0 DI data I/O-1 I/O-2 DI data I/O-3 DO data OUTPUT PLL output port INPUT I/O-3 = 0 (input port) OUT3 = 1 (OPEN or high) PLL input port Cannot be set as output port OUTPUT PLL output port INPUT PLL input port L: Reception mode H: Seek mode OPEN: RDS Unused H: Dx mode L: Lo mode When reception mode is set H: Monaural L: Stereo When seek mode is set H: SD ON L: SD OFF
The MRC sensor reads DO data from the PLL microcontroller's 6-bit A/D converter. Currently, aside from the CCB data lines, only three lines are connected to the controller microcontroller: CF/SW, AUDIO mute, and AM/FM band switching port.
Selectivity Switching Evaluation Software
Tuner processing I/O port state CF switching AUDIO mute output WIDE NARROW ON OFF Lo Lo/Dx Dx Seek mode Mode switching Reception mode RDS mode Output ON IF count Output OFF Seek
State-based Data Switching Table
Manual preset Receiving Remarks
Switchable but fixed by software Switchable but fixed by software Processing is performed according to the setting Processing is performed according to the setting I/O-3 is SD output I/O-3 is monaural/stereo output I/O-3 is SD output Seek mode RDS mode Reception mode
No. 6522-9/54
LA17000M Additional Settings (Added to the LC72144M) Output (DI)
Mode Seek mode Settings DI data IN2 I/O-0 = 1 (output port) OUT0 = 1 (Hi) DI data IN2 I/O-0 = 1 (output port) OUT0 = 0 (Lo) DI data IN2 I/O-0 = 0 (input port) OUT0 = 1 (OPEN) DI data IN2 I/O-2 = 0 (output port) OUT2 = 0 (Lo) DI data IN2 I/O-2 = 1 (output port) OUT2 = 1 (Hi) DI data IN2 I/O-0 = 1 (output port) OUT1 = 1 (Hi) DI data IN2 I/O-0 = 1 (output port) OUT1 = 1 (Lo) For seek When set
Tuner mode switch
Reception mode
For seek-stop and for receiving
RDS mode
For AF search
Lo mode Lo/Dx switch Dx mode
When setting Lo mode
When setting Dx mode
Mute ON Hard mute *1 Mute OFF
For tuning processing
When switching reception mode
Note: *1. Depends on the I/O ports usage. Input (DO)
DO data OUT data I3 = 1 (Hi) Monaural state OUT data I3 = 0 (Lo) Stereo state OUT data I3 = 1 (Hi) SD ON OUT data I3 = 0 (Lo) SD OFF OUT data ADC0 AD00 to AD05 6 bit Conditions When the tuner mode is set to reception mode *2 When the tuner mode is set to seek or RDS mode *2 Start AD conversion and then read after conversion is completed. 3.3 V at 6-bit resolution
Monaural/stereo Sensor SD
MRC output
Note: *2. I/O-3 = 0 (input port) and OUT3 = 1 (Hi) must already be set in the DI data (IN2) settings.
Other settings
In the LA17000 CF switch Pin 10 Setting Hi: Wide (wideband setting) Lo: Narrow (narrowband setting) Hi: Forced mute Lo: Mute off Lo: AM Hi: FM When set For normal operation When there is interference from adjacent frequencies When setting mute When cancelling mute For AM reception For FM reception
Soft mute (AUDIO mute) AM/FM switch
Pin 49 Pin 6
No. 6522-10/54
LA17000M Correspondence of Pins Between the LA17000M, the LA1781M, and the LC72144M
LA1781 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 26 Pin Function FN ANTD FM RF AGC FE GND FM OSC AM/FM OSC buff. FE VCC AM VCC Noise AGC-Sense Noise AGC-ADJ AM 2nd OSC Gate Out Memory circuit pin Pilot In NC, MPX GND MPX L-Out MPX R-Out Seek AM/FM SD Stop FM ST IND LA17000M Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 19 17 18 20 23 25 21 22 24 27 MRC sensor output Pilot Can. ADJ Pilot Can. ADJ MPX VCO IF count buffer and seek/stop switch GND PHASE COMP. PHASE COMP. AM/FM S-meter MRC OUT 34 35 36 37 38 39 40 41 42 43 Both I/O-3 and SD/ST-IND FMIN VDD PD1 VSS PDS XBUF I/O-2 XIN XOUT CE DI CL DO I/O-1 HCTR/I-6 I/O-0 Both ADC0 and MRC sensor output 23 16 17 18 19 20 22 8 24 1 2 3 4 5 9 11 12 7 Pin Function LC72144M Pin No.
Continued on next page.
No. 6522-11/54
LA17000M Continued from preceding page.
LA1781 Pin No. 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 64 62 63 Pin Function SNC control input HCC control input Noise canceller IN AM/FM detector output FM S-meter output MUTE drive AFC IN QD OUT CD IN VREF FMSD GND Keyed AGC VCC HCC capacitor AM L.C. Pilot detector IF AGC AM IFT (IF output) AM ANTD W-AGC IN FM Mute ON ADJ RF AGC AM 2nd MIX IN FM IF BYPASS FM IF IN AM IF IN 1st IF amplifier output AM MIX OUT W-AGC IN AM SD ADJ 1st IF IN AM RF AGC OUT N-AGC IN 1st MIX OUT 1st MIX OUT F.E.VCC FM MIX IN AM MIX IN FM MIX IN LA17000M Pin No. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1st IF narrow IN Pin Function LC72144M Pin No.
No. 6522-12/54
LA17000M PLL Block Functions * High-speed programmable divider * FMIN : 10 to 160 MHz .......................... Pulse swallower method * General-purpose counter * HCTR : 0.4 to 25.0 MHz ........................ Frequency measurement * Crystal oscillator : Two frequencies selectable: 10.35/10.25 MHz * Reference frequencies : 12 frequencies selectable: 50, 30, 25, 12.5, 6.25, 3.125, 10, 9, 3, 5, and 1kHz *1 *1 *1 *1: Not available when using the 10.25 MHz crystal oscillator * Phase comparator * Dead zone can be controlled * Unlock detection circuit * Sub-charge pump for high-speed locking * Deadlock clear circuit on chip * A/D converter ................................ 6 bits: 1 input (linked directly to MRC sensor output) * Serial data I/O Communications with controller possible in CCB format * Power-on reset circuit * On-chip crystal oscillator output buffer * 2nd IF injection signal for AM up conversion (10.35/10.25 MHz) * I/O port .......................................... General-purpose I/O: four ports
No. 6522-13/54
LA17000M Serial Data Timing
Internal data latch
Old
New
When CL is Stopped at the low level
Internal data latch
Old
New
When CL is Stopped at the high level
No. 6522-14/54
LA17000M PLL Block Pin Description
Symbol XIN XOUT Pin No. 25 26 Description X'tal OSC Function * For connecting the crystal oscillator. (10.35, 10.25, 7.2 or 4.5 MHz) Pin Circuit
PLL IN
18
Local oscillator signal input
* FMIN is selected when DVS in the serial data input is set to 1. * The input frequency range is from 10 to 160 MHz. * The signal is transmitted to the swallow counter. * The divisor can be set to a value in the range 272 to 65535. * This pin is set high during serial data input to the PLL (DI) or during serial data output (DO). * This pin is the clock for data synchronization during serial data input to the PLL (DI) or during serial data output (DO). * This is the input pin for serial data that is transferred from the controller to the PLL.
CE
27
Chip enable
CL
29
Clock
DI
28
Input data
DO
30
Output data
* This is the output pin for serial data that is transferred from the controller to the PLL.
VDD
19
Power supply
VSS I/O-1 I/O-2 STSD SW
21 31 24 17
Ground Generalpurpose I/O ports
* This is the PLL power supply pin. Supply 4.5 V to 5.5 V to this pin when the PLL is operating. * When power is first applied to this pin, the power-on reset circuit operates. * This is the PLL ground pin. * These are general-purpose I/O ports. * The output circuits open-drain. * During a power-on reset, I/O-1 and I/O-2 become input ports. STSD SW becomes an output port, and is fixed low. * These ports can be switched between input and output according to the serial data that is transferred from the controller (I/O-1, I/O-2, STSD SW). * This is a general-purpose I/O port. * The output circuits are complementary circuits. * During a power-on reset, this port becomes an input port. * This port can be specified as an input or output port by the serial data that is transferred from the controller.
SEEK SW
33
Generalpurpose I/O port
ADC0
34
ADC input * This is the A/D converter input pin. The converter is a 6-bit successive-approximation A/D converter. For details, refer to the page that describes the A/D converter configuration.
Continued on next page.
No. 6522-15/54
LA17000M Continued from preceding page.
Symbol PD1 Pin No. 20 0 Description Main charge pump output Function * This is the PLL charge pump output pin. When the frequency of the local oscillation signal frequency is divided by N is higher than the reference frequency, a high level signal is output from the PD1 pin. When the frequency is lower, a low level signal is output. If the frequencies match, the pin goes to high impedance. * A high-speed lockup circuit can be formed by using this pin in combination with the main charge pump. * For details, refer to page that describes the charge pump configuration. * Serial data: HCTR is selected if CTS1 = 1 is set. * The input frequency is 0.4 to 25 MHz. * The signal is passed through to the generalpurpose counter internally, via the 1/2 frequency divider. An integrating count can also be kept. * The count result is output from the MSB of the general-purpose counter through the output pin DO. * For details, refer to page that describes the general-purpose counter configuration. * Serial data: Prohibited when HCTR = 0. * This is the output buffer for the crystal oscillator circuit. * Serial data: When XB = 1 is set, the output buffer operates and the crystal oscillator signal (pulse) is output. When XB = 0, this pin outputs a low level. (When a power-on reset is executed, XB = 0 and the output buffer is fixed at the low level.) Pin Circuit
PDS
22
Sub-charge pump output
HCTR
32
Generalpurpose counter
XBUF
23
X'tal oscillator buffer
No. 6522-16/54
LA17000M Procedures for Input and Output of Serial Data Data I/O is handled through the Computer Control Bus (CCB), SANYO's audio IC serial bus format. This IC uses CCB with 8-bit addressing.
I/O mode [1] [2] [3] IN1 IN2 OUT Address B0 0 1 0 B1 0 0 1 B2 0 0 0 B3 1 1 1 A0 0 0 0 A1 1 1 1 A2 0 0 0 A3 0 0 0 Description * Control data input (serial data input) mode. * 32-bit data input * Control data input (serial data input) mode. * 32-bit data input * Data output (serial data output) mode. * The bit count output is equal to the clock cycle count. I/O mode setting
First Data IN1/2
First Data OUT
i) Serial Data Input (IN1/IN2)
Internal data
ii) Serial data output (OUT)
*
* *
*1: Because the DO pin is an N-channel open drain pin, the data transition time varies according to the pull-up resistance and the board capacitance. *2: The DO pin is normally open.
No. 6522-17/54
LA17000M DI Control Data (Serial Data Input) Configuration [1] IN1
Address
[2] IN2 Mode
Address
No. 6522-18/54
LA17000M Description of DI Control Data
No. Control block/Data Programmable divider data P0 to P15 Description * This data sets divisor for the programmable divider. P15 is a binary value that is designated as the MSB. The LSB changes depending on DVS and SNS. DVS 1 SNS 1 ISB P0 Divisor setting (N) 272 to 65535 Related data
(1)
* DVS = 1 (DVS = 0: Prohibited) * These values select the signal input pin (PLL IN) for the programmable divider, and switch the input frequency range. DVS, SNS DVS 1 SNS Input pin 1 PLLIN Input pin frequency range 10 to 160 MHz
* For details, refer to "Programmable Divider Configuration." Sub-charge pump control data * This data controls the sub-charge pump. PDC1 0 1 1 PDC0 * 0 1 Subcharge pump status High impedance Charge pump on (when unlocked) Charge pump on (normal operation) UL0, UL1, DLC
PDC, PDC1 (2)
* The sub-charge pump can be used to form a high-speed lockup circuit in combination with PD0 and PD1 (main charge pump). * For details, refer to the page on charge pump. Reference divider data * This is the reference frequency (fref) selection data. R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference frequency Prohibited 50 25 25 12.5 6.25 3.125 3.125 10 9 *1 5 1 9 *1 30 *1 *2 PLL INHIBIT + X'tal OSC STOP *2 PLL INHIBIT
R0 to R3 (3)
*1: Prohibited when X'tal OSC = 10.25 MHz. *2: PLL INHIBIT (backup mode) The programmable divider block stops, the PLL IN pin is pulled down to GND, and the charge pump output goes to the floating state.
Continued on next page.
No. 6522-19/54
LA17000M Continued from preceding page.
No. Control block/Data DO, I/O-5 pin control data Description * This data determines the output on the DO pin and the I/O-5 pin. ULD 0 0 0 0 DT1 0 0 1 1 DT0 0 1 0 1 DO pin Low when unlocked end-AD end-UC IN (*1) I/O-1 I/O-2 Related data
ULD DT0, DT1 IL0, IL1
end-AD: End of conversion by the A/D converter end-UC: End of conversion by the general-purpose counter
(4) Start End (I-1 changes)
*1 IL1 0 0 1 1 IL 0 1 0 1 IN Open I-1 (pin status) I-2 (pin status) If I-1 changes, DO goes low. (Note)
* However, if the I/O-1 and I/O-2 pins are specified as output ports, these pins are open. Note: Cannot be used when X'tal OSC is set to STOP. (DO does not change.) [When the reference divider data: R3 = R2 = R1 = 1 and R0 = 0] A/D converter control data * A/D converter conversion start data. ADS = 1: A/D conversion reset and start 0: A/D conversion reset ADI1 ADS ADI0 1 1 0 0 ADI0 1 0 1 0 AD input pin Stopped ADC0 Not usable Not usable
(5)
Continued on next page.
No. 6522-20/54
LA17000M Continued from preceding page.
No. Control block/Data General-purpose counter control data Description * This data sets the general-purpose counter input pin (HCTR). CTS1 1 0 CTS0, CTS1 CTE GT0, GT1 Measurement time HCTR -- Measurement mode Frequency Not measured HCTR Related data
* General-purpose counter measurement start data CTE = 1: Count start = 0: Count reset * This data determines the measurement time (frequency mode) and number of periods (period mode) for the general-purpose counter. GT1 0 0 1 1 GT0 0 1 0 1 Measurement time (ms) Frequency measurement mode Wait time (ms) CTP = 0 CTP = 1 4 3 to 4 1 to 2 8 3 to 4 1 to 2 32 7 to 8 1 to 2 64 7 to 8 1 to 2 Period measurement mode 1 period 1 period 2 periods 2 periods
(6)
CTP CTC
* CTP = 0: When a count reset is executed (CTE = 0), the general-purpose counter input is pulled down. = 1: When a count reset is executed (CTE = 0), the general-purpose counter input is not pulled down, and the wait time is reduced. However, immediately after CTP = 1 is set, the start of the count must wait until the general purpose counter input pin is biased. * The input sensitivity is reduced when CTC = 1. (Sensitivity: 10 to 30 mVrms) * This data specifies whether an I/O port is an input port or an output port. "data"= 0: Input port = 1: Output port * During a power-on reset, I/O-0 and I/O-2 become input ports. STSD SW becomes an output port. * This data determines the status of the SEEK SW pin. "data" = 0: 2.5[V] output * This pin is open and the midpoint bias is output by an external circuit. "data" = 1: 0[V] or 5[V] output * Determined by the OUT0 data. * AM/FM SD, FM-ST IND output dual-purpose pin "data" = 0: Fixed = 1: Prohibited * This data determines the output on output ports O-0 through O-3. "data" = 1: Open or Hi = 0: Low * Invalid if specified as an input port or unlocked output. * This data converts the general-purpose counter pin to an input port. HCTR = 0: Prohibited = 1: HCTR (general-purpose counter) I/O-0 to I/O-3 ULD
I/O port control data
OUT0 to OUT3 ULD
(7)
I/O-1 to I/0-2
SEEK SW (8)
(9)
SDST SW Output port data
I/O-0 to I/O-3 ULD I/O-0 to I/O-3 ULD
(10)
OUT0 to OUT2
(11)
General-purpose counter input control data HCTR
CTS1
Continued on next page.
No. 6522-21/54
LA17000M Continued from preceding page.
No. Control block/Data Unlock detection data Description * This data selects the phase error (oE) detection width that is used for evaluating PLL lock. If a phase error that exceeds the oE detection width in the following table is generated, the signal is deemed to be unlocked. When the signal is unlocked, the detection pin (DO or I/O-5) goes low. UL1 0 0 1 1 DT0 0 1 0 1 oE detection width Stop 0 0.5 s 1 s Detection pin output Open Direct output of oE Extend oE by 1 to 2 ms Extend oE by 1 to 2 ms ULD DT0, DT1 Related data
(12)
UL1, UL0
Extention
Unlocked output Crystal oscillator circuit * This is the crystal oscillator selection data. XS1 0 0 1 1 XS0 0 1 0 1 X'tal OSC Prohibited Prohibited 10.25 MHz 10.35 MHz
(13)
XS0, XS1 XB
R0 to R3
* When a power-on reset is executed, 10.25 MHz is selected. * Crystal oscillator buffer (XBUF) output control data. XB = 0: Buffer output: OFF (This mode is selected when a power-on reset is executed.) XB = 1: Buffer output ON * For FM reception (using the PD0 pin), XBUF output must be off. * This data controls the phase comparator dead zone. DZ1 0 0 1 1 DZ0 0 1 0 1 Dead zone mode DZA DZB DZC DZD
Phase comparator control data (14) DZ0, DZ1
* When a power-on reset is executed, DZA is selected. Charge pump control data (15) DLC * This data is used to force the charge pump output to the low level (VSS level). DLC = 1: Low level = 0: Normal operation * If a deadlock occurs because the VCO control voltage (Vtune) is 0 V and VCO oscillation is stopped, it is possible to escape the deadlock by forcing the charge pump output to low level and setting Vtune to VCC. When a power-on reset is executed, normal operation mode is selected. * This is the IC test data. Set TEST0 = 0. TEST1 = 0 TEST2 = 0 * When a power-on reset is executed, all the test data is set to zero.
IC test data (16) TEST0 TEST1 TEST2
No. 6522-22/54
LA17000M DO Output Data (Serial Data Output) Configuration [3] OUT mode
Address
: "0" data
No.
Control block/Data I/O port data
Description * I0 to I3 is the latched data reflecting the status of the input ports: I/O-0 to I/O-3. The data is latched at the point that data output mode is set. The pin status is latched regardless of the input/output specification. Pin status = Hi: 1 Low: 0 * C19 to C0 is the latched data reflecting the contents of the general-purpose counter (a 20-bit binary counter). C19 C0 MSB of binary counter LSB of binary counter
Related data I/O-1 to I/O-2 SEEK SW HCTR
(1)
I3 to I0
(2)
General-purpose counter binary data C19 to C0 A/D converter ADC0 data AD05 to AD00
CTS0 CTS1 CTE
(3)
* AD05 to AD00 is the latched data reflecting the results when the ADC0 pin input signal undergoes AD conversion. AD05 AD00 MSB LSB
ADI1 ADS
No. 6522-23/54
LA17000M Programmable Divider Configuration
DVS SNS (A) 1 *
Input pin PLL IN
Divisor setting (N) 272 to 65535
Input frequency range 10 to 160 MHz
Minimum input sensitivity f[MHz] (A) PLL IN 10 f < 130 40 mVrms 130 f <160 70 mVrms
General-purpose Counter Configuration In the LA17000M, the general-purpose counter consists of a 20-bit binary counter. The count results can be read through the DO pin, MSB first.
General-purpose counter (20-bit binary counter)
DO pin
When using the general-purpose counter for cycle measurement, the measurement period can be selected from among 4, 8, 32, and 64 ms through the GT0 and GT1 data. The cycle of the signal that is input to the HCTR pin or the LCTR pin can then be measured by counting the number of pulses that are input to the general-purpose counter within this measurement period. When using the general-purpose counter to measure a cycle, it is also possible to measure the cycle of a signal that is input to the LCTR pin according to the number of check signals (refer to the "Check Signal Frequency" table below) input to the general-purpose counter within one or two cycles of the signal that is input to the LCTR. Check Signal Frequency
X tal OSC Check signal 10.25 MHz 10.25 kHz CTS1 S1 1 Input pin HCTR 10.35 MHz fref = 30, 9, 3 kHz 1030 kHz Measurement mode Frequency fref other than 30, 9, 3 kHz 1150 kHz Frequency range 0.4 to 25.0 MHz Input sensitivity 40 mVrms *1
*1 CTC = 0: 40 mVrms; however, when CTC = 1, the frequency range is HCTR: 8 to 12 MHz CTC = 1: 70 mVrms
No. 6522-24/54
LA17000M CTC data: This is the input sensitivity switch data; when CTC = 1, the input sensitivity is degraded.
HCTR: Minimum input sensitivity standard f [MHz] CTC 0 (Normal mode) 1 (Degraded mode) 0.4 f < 8 40 mVrms 8 f < 12 40 mVrms (1 to 10 mVrms) 70 mVrms (30 to 40 mVrms) 12 f < 25 40 mVrms
--
--
--: Not stipulated (operation not guaranteed) ( ): Actual performance estimates (reference value)
CTP data: This is data that determines the status of the general-purpose counter input pin (HCTR/LCTR) when a general-purpose counter reset (CTE = 0) is executed. CTP = 0: Pulls down the general-purpose counter input pin. = 1: Does not pull down the general-purpose counter input pin, reducing the wait time to 1 or 2 ms. When setting CTP = 1, do so at least 4 ms prior to starting the count (CTE = 1). If the counter is not to be used, set CTP = 0.
GT1 0 0 1 1 GT0 0 1 0 1 Measurement time Frequency measurement mode Wait time CTP = 0 CTP = 1 4 ms 3 to 4 ms 8 1 to 2 ms 32 7 to 8 ms 64 Cycle measurement mode 1 cycle 2 cycles
IF Counter Operation Before starting counting with the general-purpose counter, the general-purpose counter must first be reset by setting CTE = 0. The general-purpose counter is made to start counting by setting serial data CTE = 1. The serial data is finalized within the PLL by changing CE from high to low, but input to the HCTR pin must be started within the wait period after CE is sent low at the very latest. After measurement ends, the count results from the general-purpose counter must be read while CTE = 1. (Once CTE is set to zero, the general-purpose counter is reset.) Furthermore, the signal that was input to the HCTR pin is passed through to the general-purpose counter after having been divided by 1/2 internally. Therefore, the general-purpose count results are actually 1/2 the actual frequency of the signal that was input to the HCTR pin.
CTE = 1 data Wait time Frequency measurement time Measurement time 40 mVrms or more* (when measuring frequency) * CTC = 0: 40 mVrms CTC = 1: 70 mVrms
Signal input
No. 6522-25/54
LA17000M Integrated Count
Internal data latch (CTE)
GT
General-purpose counter
(integration)
end-UC Count end
* General-purpose counter reset * General-purpose counter start * Setting to "1" again causes a restart. When using integrated counting, the count value is accumulated in the general-purpose counter. Be careful about counter overflows. Count value: 0H to FFFFFH (1048575) When using integrated counting, resending serial data (IN1) with CTE = 1 restarts measurement with the general-purpose counter, and the count results are added to the previous count results.
* CTE: 0 1
A/D Converter Configuration This is a 6-bit successive-approximation converter with a conversion time of 0.56 ms. Full scale (when the data is 3FH) is (63/96) x VDD.
Multiplexer
Evaluation circuit Comparator
Decoder
REGISTER DO pin : "0" data
No. 6522-26/54
LA17000M
ADI1 1 1 0 0 ADI0 1 0 1 0 Input pin Prohibited ADC0 Prohibited Prohibited * Since the PLL block in the LA17000M does not provide an external pin for ADI1, the function cannot be used. ADI0 is linked directly to the pin 34 MRC sensor output, and is used exclusively for multipath signal intensity detection.
Conversion
Conversion end
Conversion start
Charge Pump Configuration
D0, I/O-5 pin
PDC1 PDC0 0 1 1 * 0 1
PDS (sub-charge pump status) High impedance Charge pump on (when unlocked) Charge pump on (at all times)
DLC 0 1
PD1, PDS Normal operation Forced low
If the unlocked state is detected during a channel change, the PDS (sub-charge pump) operates, R1 R1M/R1S, the low-pass filter time constant is reduced, and lockup is accelerated.
* Unlock detection data: UL1 = 1 must be set. This sets the unlock detection width to "0.5 s" or "1 s" mode; if a phase difference that is greater than the value in question is detected, the signal is unlocked and the sub-charge pump operates. As the locked condition is approached and the phase difference falls to less than the unlocked detection width, the sub-charge pump stops operating (goes to high impedance).
No. 6522-27/54
LA17000M Other Items [1] Notes on the Phase Comparator Dead Zone
DZ1 0 0 1 1 DZ0 0 1 0 1 Dead zone mode DZA DZB DZC DZD Charge pump ON/OFF ON/ON OFF/OFF OFF/OFF Dead zone - -0 s -0 s +0 s ++0 s
Since correction pulses are output from the charge pump even if the PLL is locked when the charge pump is in the ON/ON state, the loop can easily become unstable. This point requires special care when designing application circuits. The following problems may occur in the ON/ON state. * Side band generation due to reference frequency leakage * Side band generation due to both the correction pulse envelope and low frequency leakage Schemes in which a dead zone is present (OFF/ON) have good loop stability, but have the problem that acquiring a high C/N ratio can be difficult. On the other hand, although it is easy to acquire a high C/N ratio with schemes in which there is no dead zone, it is difficult to achieve high loop stability. Therefore, it can be effective to select DZA or DZB, which have no dead zone, in applications which require an FM S/N ratio in excess of 90 to 100 dB, or in which an increased AM stereo pilot margin is desired. On the other hand, we recommend selecting DZC or DZD, which provide a dead zone, for applications which do not require such a high FM signal-to-noise ratio and in which either AM stereo is not used or an adequate AM stereo pilot margin can be achieved. Dead Zone The phase comparator compares fp to a reference frequency (fr) as shown in Fig. 1. Although the characteristics of this circuit (see Fig. 2) are such that the output voltage is proportional to the phase difference o (line A), a region (the dead zone) in which it is not possible to compare small phase differences occurs in actual ICs due to internal circuit delays and other factors (line B). A dead zone as small as possible is desirable for products that must provide a high S/N ratio. However, since a larger dead zone makes this circuit easier to use, a larger dead zone is appropriate for popularlypriced products. This is because it is possible for RF signals to leak from the mixer to the VCO and modulate the VCO in popularly-priced products in the presence of strong RF inputs. When the dead zone is narrow, the circuit outputs correction pulses and this output can further modulate the VCO and generate beat frequencies with the RF signal.
Leak
Fig. 1 Fig. 2 [2] Notes on the PLL IN and HCTR pins Coupling capacitors must be placed extremely close to these pins. The capacitance should be about 100 pF. If a capacitor with a capacitance of 100 pF or less is not used with HCTR in particular, there will be a long wait until the bias level is reached, which may sometimes cause miscounting. [3] Notes on IF counting When using the general-purpose counter for IF counting, be certain to have the microcontroller determine whether the IF-IC SD (Station Detector) signal is present or not, and to turn on the IF count buffer output and conduct the count, but only if the SD signal is present. Conducting an auto search using only the IF count is not reliable, since there is a possibility of stopping even where there is no station due to leaked output from the IF count buffer. [4] Using the DO pin Aside from data output mode, the DO pin can also be used to check for the completion of counting by the generalpurpose counter, unlock detection output, and to check for changes in the input pins. It is also possible to input the status of the input pins (I/O-1, I/O-2) to the controller, unchanged, via the DO pin.
No. 6522-28/54
LA17000M [5] Cautions concerning the use of XBUF When the XBUF output is on (AM up conversion is being used), the XBUF signal may leak to the adjacent pins (PD0, I/O-3), so do not use PD0 and I/O-3 for AM reception control. (Use the PD1 pin for the AM reception charge pump.) When using PD0 and I/O-3 for FM reception control, the XBUF output must be turned off (XB data = 0). [6] Power supply pins To filter out noise, insert a capacitor of at least 2000 pF between the power supply pins VDD and VSS. The capacitor must be located as close to the pins as possible. Tuner Block Pin Description
Pin No. 1 Function Antenna damping drive pin. Equivalent circuit Pin 62 Description The antenna damping current flows to this pin when the pin 2: RF AGC voltage is VCC-VD.
A13328 2 RF AGC FET 2nd gate voltage control pin.
A13329 3 4 F.E.GND OSC OSC pin with built-in Tr. capacitor for oscillator circuit.
A13330
Continued on next page.
No. 6522-29/54
LA17000M Continued from preceding page.
Pin No. 6 Function F.E.VCC, AM/FM switch pin
AM/FM Switch Circuit
Equivalent circuit
Description Pin 6 is shared for FM F.E.VCC and the AM/FM SW circuit. V6 voltage 8V OPEN Mode FM AM
A13366 7 AM OSC First OSC for AM. Permits oscillation up to the SW band. ALC circuit connected.
A13331 8 9 Noise AGC sensitivity AGC adjusting pin Pin 8 is the noise sensitivity setting pin. After setting a moderate field (approximately 50 dB), use the pin 9 AGC adjusting pin to make the setting for weak fields (approximately 20 to 30 dB).
A13332 10 AM 2nd OSC Shared pin. CF selectivity switch. Select either 10.7 MHz 1st IF input pin 72 or pin 78. * A second local oscillation signal is injected by the PLL XBuffer. * The PLL X'tal is as follows: AM 9 kHz step 10.35 MHz AM 10 kHz step 10.25 MHz (NDK AT-51 type: XTAL oscillator)
SWON pin 78 input SOWOPen pin 78 input
A13367
Continued on next page.
No. 6522-30/54
LA17000M Continued from preceding page.
Pin No. 11 12 Function Memory circuit pin Memory circuit pin Equivalent circuit Description Memory circuit used when the noise canceller is in operation.
Differential amp
Gate circuit
A13333 13 Pilot input Pin 13 - PLL circuit signal input pin.
A13334
14 15 16
N.C, MPX, MRC, GND MPX output (LEFT) MPX output (RIGHT)
GND for N.C/MPX/MRC circuit. De-emphasis 50 s; 0.015 F 75 s; 0.022 F
A13335
Continued on next page.
No. 6522-31/54
LA17000M Continued from preceding page.
Pin No. 17 Function SD pin Stereo indicator Equivalent circuit Description For FM: V17 switches among three modes according to the following voltages. 5 V: Operates in conjunction with the SD pin and the IF count buffer. 2.5 V:Operates as SD pin in forced SD mode. RDS AF9AR. 0 V: Reception mode stereo indicator For AM: (two modes: 0 and 5 V) 5 V: Operates as SEEK SD pin. 0 V: Reception mode, not used A13342 35 Pilot canceller signal input The pilot signal level requires adjustment since it changes according to variations in the IF output level, etc.
AM/FM SD
Stereo indicator
SEEK/STOP switch
A13336 36 Pilot canceller signal output Pin 36 pilot canceller signal output pin.
A13337
Continued on next page.
No. 6522-32/54
LA17000M Continued from preceding page.
Pin No. 37 VCO Function Equivalent circuit Description Oscillation frequency: 912 kHz. Murata CSB912JF108
A13338 40 41 PHASE COMP. PHASE COMP.
A13339 38 IF count buffer SEEK/STOP switch Shared pin for the IF count buffer (AC output) and SEEK/STOP switch (DC input). V38 switches among three modes according to the following voltages. For FM: 5 V: SEEK mode 2.5 V: Forced SD mode, RDS mode 0 V: Reception mode For AM (two modes: 0 and 5V) 5 V: SEEK mode 0 V: Reception mode *When interference from an adjacent FM frequency is detected: 2.5 V: Use RDS mode.
IF count buffer
SD circuit
Forced SEEK SD 2.5V 5V
A13340
Continued on next page.
No. 6522-33/54
LA17000M Continued from preceding page.
Pin No. 42 Function AM/FM S-meter Equivalent circuit Description Constant current drive-type S-meter output.
FM S-meter
48
Dedicated FM S-meter
AM S-meter
When AM is set, pin 48 outputs a 1 mA current, which turns HCC OFF.
AM/FM SW
A13341 43 MRC control voltage time constant The MRC detection time constant is determined 1 k and C2 when discharging and by a constant current of 7 A and C2 when charging.
to pin 44
A13343 44 SNC control input pin Controls sub-output with an input of 0 to 1 V. SNC voltage is determined by the RA and RB component voltage. This sets the separation blend curve. RB = 5 k on chip RA is external
A13344 45 HCC control input pin Controls high frequency output with an input of 0 to 1 V. Control through the MRC output is also possible. Use at least a 100 k resistor when using pin 48 FM S-meter for control.
A13345
Continued on next page.
No. 6522-34/54
LA17000M Continued from preceding page.
Pin No. 46 Function Noise canceller input
FM detection output
Equivalent circuit
Description Pin 46: N.C. input Input impedance 50 k Pin 47: AM.FM detection output For FM: Low impedance For AM: 10 k output To improve low-band separation, use a coupling capacitor of at least 10 .
47
AM/FM detection output
AM detection
A13346 48 IF S-meter output and MRC DC input pin FM S-meter output block MRC AC input block Adjust an external 1-k resistor to attenuate and control the MRC AC input.
MRC input
A13347 49 Mute driver output 1) The mute time constant is determined by an external CR as follows: Attack time TA = 10 k x C1 Release time TR = 50 k x C1 2) Noise convergence adjustment Fine adjustments can be made when there is no input to the ANT input by inserting a resistor between pin 49 and GND.
BAND MUTE
SD circuit
3) Mute off function Short pin 49 with GND using a 4-k resistor.
A13348
Continued on next page.
No. 6522-35/54
LA17000M Continued from preceding page.
Pin No. 50 51 52 53 Function AFC QD output QD input VREF Equivalent circuit Description * R1: Resistor that determines the band muting function. Increasing the value of R1 narrows the band Reducing the value of R1 widens the band. * Null voltage Voltage between pins 50 and 53 during tuning: V50-53 = 0 V Band muting turns on when |V50-53| 0.7 V. V53 = 4.9V
Quadrature detection
1F limiter AMP
BAND MUTE
A13349 54 FM SD Adi Current of 130 A flows from pin 54 and comparison voltage is determined by external resistance.
Comparator S-meter
A13350 The keyed AGC operates when the voltage divided by the 6.4-k and 3.6-k resistors on S-meter output pin 42 falls below the voltage determined by the resistor between pin 55 and GND. Shared pin for the AM stereo decoder IF buffer.
55
Keyed AGC AM stereo buffer
S-meter
Comparator
A13351
Continued on next page.
No. 6522-36/54
LA17000M Continued from preceding page.
Pin No. 57 Function HCC capacitor Equivalent circuit Description HCC frequency characteristics are determined by the capacitance of the external capacitor.
A13352 58 AM L.C. pin In AM mode, this changes the frequency characteristics of the unneeded audio band below 100 Hz in order to produce clear audio. Note: The capacitor for the LC must be connected to VCC (pin 56) (because the detection circuit operates with VCC as a reference). The cutoff frequency fC is determined by the following formula: A13353 59 Pilot detector fC = 1/2 x 50 k x C Inserting a 1-M resistor between pin 59 and VCC forces MONO.
A13354
Continued on next page.
No. 6522-37/54
LA17000M Continued from preceding page.
Pin No. 60 Function IF AGC Equivalent circuit Description Q1: Seek time constant switch = 2.2 F x 300 k 2 SEEK = 2.2 F x 10 Connect external C to VCC (because the IF amplifier operates with VCC as a reference).
A13355 61 IF output Pin56 VCC IF amplifier load
Pin56 VCC
A13356 62 AM ANT damping drive output Wideband AGC input I62 = 6 mA max ANT damping current
A13357
Continued on next page.
No. 6522-38/54
LA17000M Continued from preceding page.
Pin No. 63 Function FM mute on Adjust Equivalent circuit Description Vary the external resistor to adjust the mute on level.
Inverter circuit
A13358 64 73 RF AGC bypass RF AGC RF AGC rectification capacitor The distortion in low-frequency modulation is determined as follows. C64, C73 Increase Distortion Good Response Slow
Antenna damping
C64, C73 Decrease Distortion Worsens Response Fast
For AGC
A13359 66 IF bypass Be careful in regards to the GND point for the limiter amplifier input C. Ground C1 at a point that does not increase AMR.
67
FM IF input
A13360 68 IF input Input impedance 2 k
A13361
Continued on next page.
No. 6522-39/54
LA17000M Continued from preceding page.
Pin No. 69 72 78 Function IF amplifier output IF amplifier input wide input IF amplifier input narrow input Equivalent circuit Description * 1ST.IF amplifier I/O pin * Inversion amplifier V78 = 2 V Narrow 1st IF input V72 = 2 V Wide 1st IF input Input impedance RIN = 330 V59 = 5.3 V Output impedance ROUT = 330 When SW1 open, SW2 short When SW1 short, SW2 open Switched by the CF band, switched by voltage on pin 10. Wire the MIX coil that is connected to the pin 70 MIX output to pin 56 (VCC). Pin 65 MIX input. Input impedance 330
A13362 70 65 MIX output 130 A MIX input Pin 56 VCC VCC pin 56
A13363 71 W-AGC IN AM SD Adjust N-AGC IN mute attenuation adjusting pin Pin 77 VCC Pin 71, 74 DC cut capacitors are on chip. The AGC on level is determined by the capacitance of C1 and C2. Pin 71 is the SD sensitivity adjusting pin for AM. Output current I71 = 50 A, and V71 varies according to the external resistance. SD is put into operation by comparing V71 with the S-meter voltage.
74
S-meter
A13364
Continued on next page.
No. 6522-40/54
LA17000M Continued from preceding page.
Pin No. 75 76 80 Function MIX ouput MIX input Equivalent circuit Description Double-balance type mixer Pins 75 and 76, MIX output, 10.7 MHz output Pin 80, MIX input Emitter injection method and injection amount are determined by the values of C1 and C2. Note: The line for pin 80 must not approach pins 75 and 76.
A13365 79 1st MIX INPUT 1st MIX input Input impedance: approximately 10 k
A13368
No. 6522-41/54
LA17000M Methods for Using the LA17000M (1) About VCC and GND
Pin 56 Pin 39 Pin 14 Pin 77 *Pin 6 Pin 3 VCC for FM IF, AM, NC, MPX, and MRC GND for FM IF and AM GND for NC, MPX and MRC VCC for FM FE, AM 1st MIX, and 1st OSC VCC for FM FE and AGC, and AM/FM switch GND for FM FE, AM 1st MIX, and 1st OSC
(2) Notes on AM coil connection VCC for the 1st OSC coil that is connected to pin 7 should have the same electric potential as pin 77. Connect pin 61 IFT to pin 70 MIX coil. VCC should have the same electric potential as pin 56. (3) AM/FM switch Pin 6 serves as FM, FE, and RFAGC VCC.
Pin 6 voltage 8 OPEN
Mode FM AM
(4) Relationship between pin 38 and pin 17 4-1. For FM Pin 17 STEREO indicator and SD dual-purpose pin Pin 38 DC input SEEK, STOP pin (control pin) AC output IF count buffer pin
IF count buffer 0 to several k
SW1 OPEN ON --
SW2 OPEN OPEN ON
Pin 38 voltage 5V 2.5 V 0.7 V or less
Pin 17 IF count buffer on IF count buffer on OFF
Pin 17 SD High-speed SD Stereo indicator
Relationship Between Pin 38 Control Method and Output from Pins 38 and 17
No. 6522-42/54
LA17000M Relationship between FMSD, IF count buffer output, S-meter, and mute drive output
S-meter R38 larger
R38 smaller
V49 0.7 V or more V49 0.7 V or more
ON as SD
Stereo
Monaural
IF count buffer on
IF count output ON
Note: IF count output is off in the LA1780/81. Turn the IF count output on in the LA17000M only. (This is done for use in detecting interference from adjacent frequencies.)
Switch this mode for use in SD detection in RDSAF search, etc. Use 2.5 V mode for detecting interference from adjacent frequencies, and confirm the IF count frequency.
About FM SD
Band mute Mute drive output
Smeter
IF count buffer Connected directly to PLL and I/O-3
IF count output
No. 6522-43/54
LA17000M 4-2. For AM
S-meter
R71 larger R71 smaller
Pin 71 AM, SD, Adj Pin
(5) AM STEREO support pin
To AM ST decoder 400 mVrms 450 kHz output
* To attenuate the pin 55 AC level, add capacitance between GND and pin 55. For example, if pin 67 is added between GND and pin 55, the AM IF output decreases by about 6 dB.
No. 6522-44/54
LA17000M (6) About MUTE ATT It is possible to switch to one of three levels (-20 dB, -30 dB, or -40 dB) by means of the resistor between pin 74 and GND. (This also has an effect on the total gain of the tuner.)
R OPEN 200 k 30 k Mute ATT -20 dB -30 dB -40 dB
The attenuation can be reduced as shown in the table above by reducing R49.
MUTE time constant Attack 10 k x C49 Release 50 k x C49
Quadrature detector
Limiter
No. 6522-45/54
LA17000M (7) MRC circuit
S-meter
FM S-meter
The stereo blend curve can be adjusted through the R28 external resistor.
1) When there is no AC noise on pin 48 V42 = V43-VBE QMRC V43 is approximately 2.5 V when ANT input is 60 dB or higher. 2) Because the MRC noise amplifier gain is fixed, adjust MRC by reducing the AC input level.
3) The MRC attack and release are determined by C43 on pin 43. Attack 7 A * C27 Release 500 * C27
(8) FM soft mute
R63 smaller
R63 larger
R63 larger
R63 smaller
Compare the pin 63 MUTE ON adjusting voltage and the V42 S-meter voltage, and adjust the MUTE ON point.
No. 6522-46/54
LA17000M (9) About the noise canceller The noise canceller improves the characteristics by implementing the circuits that determine the gate time with a logic circuit. Because a conventional noise canceller determines the time constant according to CR as shown in Fig. 5, the rise time is dependent on the CR, as shown in Fig. 6. This caused a delay in the rise, which resulted in a deterioration of noise filtering performance when the rise was delayed too much. In the LA17000, the circuits that determine the gate time have been configured with logic, resulting in a faster rise and making more reliable noise filtering possible.
No. 6522-47/54
LA17000M
Block Diagram
33k
0.022F
33k 56k 82k
0.01F
10F
560
0.022F
12k
30k
100F
2.2F
0.1F 0.22F
1000pF
1F
10k QD OUT 10k QD IN
+
0.47F
2200pF
+
+
10k
24k IF AGC PILOT DET AM LC
1F
1F
0.47F
+
62k
+
+
1F
+
+
+
0.22F
SEP ADJ
AM (STEFEO) IF OUT MUTE OFF(RDS)
+
60
AM DET 33 0.022F AM ANTD WIDE AGC FM MUTE ON ADJ 11k RF AGC
+ +
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
+
1F 5.6k
C. HCC
VCC
KEYED AGC
FM SD
VREF
AFC IN
MUTE FM DRIVE S-METER
DET OUT
NC
50k HCC
SNC
MRC OUT
AM/FM S-METER
To microcontroller PHASE COMP
+
61 62 63 64 65 66 67 68 69 70 MIX MRC RF AGC WB AGC TWEET 12Bits PROGRAMMABLE DIVIDER SWALLOW COUNTER 1/16,1/17 4Bits REFERENCE DIVIDER F.E REG FM/AM SWICH --+ CCB I/F DET L.C. IF BUFFER OC-C DET AFC CI AMP ANT D OSC BUFF OSC Q.DET MUTE AMP.
40 39 38 F.F.19k 90 VCO STOP PILOT DET. TRIG VCO 37
MPX VCO GND
0.022F
470
1MH
HCC SNC
F.F.19k 90
PHASE COMP.
IF COUNT BUFF SEEK/STOP switch
100H FC18
HOLE DET
MUTE DRIVE
100H
CSB912TF108
0.022F
100k
100H
47F
15pF
15pF
VSM SHIFTER 51k
3.3F 2nd MIX IN FM IF BYPASS
0.022F
510
0.022F
FM IF IN
300
IF LIMIT AMP. BUFF IF AGC AM SM AM SD FM SM FM SD
35 F.F.30k 0 F.F. PILOT CAN. 34
Pdot C 0.01F ADJ 100k 0.47F 5V
100k
36
0.22F
MRC SENOR AUTO ADJ
47k 47k
UNTVERSAL COUNTER
33 32
SEEKSW
47k
HCTR 100pF I/O-1 51k
I/O-1
1st IF OUT
DATA SHIFT REGISTER LATCH 31 30 29 28 27 26 25
AM MIX OUT
100k
1st IF IN
72 73 74
CL
CF SW
AM RF AGC OUT
AM/FM VREF HPH W.B AGC RF AGC Keyed AGC LPF
DI
150
62pF N-AGC IN MUTE ATT ADJ
CE X' OUT 24pF 10.25 MHz X' IN 24pF 51k
75 76 77 78 79
30
15 MIX OUT FE VCC 1st IF Narrow IN
0.022F
MIX
BUFF BUFF AM 1ST OSC AGC TRIG GATE MAIN HC SUB DEC MAT RIX POWER ON RESET 24
I/O-2
0.022F
30
8pF
+
100F
AM 1st MIX IN 0.022F 5pF FM MIX IN
23 PHASE DETECTOR CHARGE PUMP 9
NC AGC
+
XBUFF
22 21
PDS PLL VSS
1000pF
100k
18pF
1000pF
80
ANT D 1 2
FM RF AGC
OSC
1000pF
1000pF
220
37pF
3
FE GND 30k FM OSC
4
5
6
AM/FM SW
7
AM OSC
8
NC Sens
10
0.47F
AM OSC
11
Gore OUT 6800pF
12
13
MPX Pdot IN 0.01F
14
15
0.015F
16
0.015F
17
SD ST-IND
18
PLL IN
19
100pF
20
PD1 10k
+
200k
0.01F
1F
FM ANTD
0.01F
6pF
100k
10k
5V
0.022F
3.3F
0.022F
5pF
30k
300pF
0.1F
100
+
0.022F
10k
0.22F
10pF
350
30pF 30k
51k
150pF
AM VCC AM ANT IN FM BF GND FM ANT IN
NC MPX GND
10k
22k
0.022F
VCC=8V
CF SW
L-CH
R-CH
PLL VDD=5V
FMIF AMNC FM/AM FMIF AM MPX VCC VT GND
100k
1M
SEEKAM/FM SD STOPFM ST IND SDSTSW
micro contlorrer
A13385
AM SD ADJ 71 WIDE AGC IN
DO
No. 6522-48/54
LA17000M Recommended External Components
Component name AM loading coil AM ANT-IN AM RF LPF AM choke coil AM 2nd MIX coil AM IF coil AM OSC1 coil AM/FM MIX coil with selectivity switch AM/FM MIX coil without selectivity switch FM detection coil FM OSC coil FM RF coil FM ANT coil MPX ceramic oscillator PLL X'tal oscillator FM ceramic filter FM/AM narrow band ceramic filter AM ceramic filter AM pin diode AMRF FET+TR AM OSC1 varactor FM pin diode FM RF amplifier FET FM RF/ANT/OSC varactor Manufacturer Toko Sumida Electronics Co., Ltd. Toko Sumida Electronics Co., Ltd. Toko Sumida Electronics Co., Ltd. Toko Sumida Electronics Co., Ltd. Toko Sumida Electronics Co., Ltd. Toko Sumida Electronics Co., Ltd. Toko Sumida Electronics Co., Ltd. Toko Sumida Electronics Co., Ltd. Toko Sumida Electronics Co., Ltd. Toko Sumida Electronics Co., Ltd. Toko Sumida Electronics Co., Ltd. Toko Sumida Electronics Co., Ltd. Toko Murata Manufacturing Co., Ltd. Kyocera Nihon Dempa kogyo Murata Manufacturing Co., Ltd. Murata Manufacturing Co., Ltd. Toko Murata Manufacturing Co., Ltd. SANYO Electric Co., Ltd. SANYO Electric Co., Ltd. SANYO Electric Co., Ltd. SANYO Electric Co., Ltd. SANYO Electric Co., Ltd. SANYO Electric Co., Ltd. Component number L1 L2 L3 L4 L7 L8 L9 L10 L10 L14 L11 L12 L13 VCO1 VCO2 CF1 CF2 CF3 PIN1 FET1 VD2 PIN2 FET2 VD3 Component model number 7TL-269ANS-0720Z SA-1062 7PSU-385BNS-027Z SA-1048 5VUS-A286LBIS-15327 SA-1051 8RB-187LY-222J RC875-222J 5PG-5PGLC-5310N SA-264 7PSGTC-50002Y=S SA-1063/SA-1112 7KSS-V666SNS-213BY SA-359 7PSG-8261N-5202D=S SA-266 371DH-1108FYH SA-208 DM600DEAS-8407GLF SA-125 (JP), SA-278 (US) T-666NF-251APZ (JP), T-666SNF-2471B (US) SA-143 (JP), SA-250 (US) T-666NF-269X (JP), T-666SNF-246JA (US) SA-144 (JP), SA-231 (US) T-666NF-268Z (JP), T-666SNF-244X (US) CSB912JF108 (912 kHz) KRB-912F108 (912kHz) LN-P-0001 (10.25, 10.35 MHz) SFE 10.7MS3A50K-A SFE 10.7 MTE LFCM450H SFPS450H 1SV234/267 FC18 SVC252/253 1SV234 3SK263/264 SVC231/208
No. 6522-49/54
LA17000M Crystal oscillator Nihon Dempa Kogyo Co., Ltd. Frequency: 10.25 MHz CL: 16pF Model name: LN-P-0001 Coil specifications Sumida Electronics Co., Ltd. [AM block] AM FILTER (SA-1051)
10.35 MHz 16pF LN-P-0001
AM OSC (SA-359)
AM IF1 (SA-264)
AM IF2 (SA-1063)
AM loading (SA-1062)
AM ANT IN (SA-1048)
For AM RF amplifier (RC875-222J)
[FM block] FM RF (SA-1060)
FM ANT (SA-1061) (without selectivity switch)
FM OSC (SA-1052)
FM MIX (SA-266)
FM DET (SA-208)
No. 6522-50/54
LA17000M TOKO Co., Ltd. [AM block] AM FILTER (A286LBIS-15327)
AM OSC (V666SNS-213BY)
AM IF1 (7PSGTC-5001A=S)
AM IF2 (7PSGTC-5002Y=S)
AM loading (269ANS-0720Z)
AM ANT IN (385BNS-027Z)
For AM RF amplifier (187LY-222)
[FM block] FM RF (V666SNS-208AQ)
FM ANT (V666SNS-209BS)
FM OSC (V666SNS-205APZ)
FM MIX (371DH-1108FYH) (without selectivity switch)
FM DET (DM600DEAS-8407GLF)
FM MIX (826IN-5202D=S) (with selectivity switch) External 82P2 in parallel (1-G, 3-G)
No. 6522-51/54
LA17000M FM I/O Characteristics AM I/O Characteristics
AF output, noise - dB
ANT input, IN - dB AM2 Signal Interference Characteristics
AF output, noise - dB
ANT input, IN - dB AM2 Signal Interference Characteristics
AF output, noise - dB
ANT input, IN - dB FM Antenna input Temperature Characteristics (1)
Total harmonic distortion, THD - %
Ambient temperature, Ta - C FM Antenna input Temperature Characteristics (3)
Separation, Sep -- dB
AF output, noise - dB
ANT input, IN - dB FM Antenna input Temperature Characteristics (2)
Ambient temperature, Ta - C FM Antenna input Temperature Characteristics (4)
S-meter voltage, VSM -- V
Ambient temperature, Ta - C
Ambient temperature, Ta - C
No. 6522-52/54
LA17000M FM Antenna input Temperature Characteristics (5) FM Antenna input Temperature Characteristics (6)
Ambient temperature, Ta - C FM Antenna input Temperature Characteristics (7)
Output voltage, VO - dBm
Ambient temperature, Ta - C
Total harmonic distortion, THD - %
Ambient temperature, Ta - C AM Antenna input Temperature Characteristics (1)
AM Antenna input Temperature Characteristics (2)
Ambient temperature, Ta - C AM Antenna input Temperature Characteristics (3)
S-meter voltage, VSM -- V
Ambient temperature, Ta - C AM Antenna input Temperature Characteristics (4)
Ambient temperature, Ta - C
SD sensitivity, SD - dB
Ambient temperature, Ta - C
No. 6522-53/54
LA17000M AM Antenna input Temperature Characteristics (5) AM Antenna input Temperature Characteristics (6)
Ambient temperature, Ta - C AM Antenna input Temperature Characteristics (7)
Ambient temperature, Ta - C
Output voltage, VO - dBm
Ambient temperature, Ta - C
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of June, 2001. Specifications and information herein are subject to change without notice.
No. 6522-54/54

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